In the prior art, there is the wiring substrate which is applied as the semiconductor package for mounting the semiconductor chip. Such wiring substrate is manufactured based on laminating the wiring layers on the substrate by means of the build-up method.
In Patent Literature 1 (Japanese Laid-open Patent Publication No. 2005-244108), it is set forth that, in the wiring substrate which has the pads in the openings of the dielectric layer on its surface, the wall surface conductor portion which is formed from the outer edge of the pad main body to the inner layer direction, along the wall of the opening portion, is provided on the back surface side of the pad, thereby the crack which is generated from the boundary between the pad and the dielectric layer as the starting point should be prevented.
In Patent Literature 2 (Japanese Laid-open Patent Publication No. 2007-13092), it is set forth that the wiring substrate is obtained by forming to laminate the electrodes and the wiring portions connected thereto on the supporting substrate, and then removing the supporting substrate.
As explained in the column of the related art described later, the connection pads (copper pad) of the wiring substrate on which the semiconductor chip is mounted are mounted on the mounting substrate via the solder bumps, and thus the electronic component module is constructed. In such electronic component module, particularly in the case that the wiring substrate is the coreless type, when the drop test is performed as a reliability test, a crack is easily generated from the periphery of the connection pad to the inner layer side. Therefore, such a problem arises that sufficient reliability cannot be obtained in use.